STNoC addresses one of the most critical issues in SoC technology, which is the interconnection between the many IP blocks that make up the SoC device. Typically, these include one or more high performance processor cores as well as complex, dedicated IP blocks such as audio/video codecs, a wide range of connectivity IPs (USB, Ethernet, serial ATA, DVB-H, HDMI etc), and memories. Up till now, the interconnection between these blocks has been implemented via traditional circuit-switched buses but it has been widely accepted in recent years that a new interconnection methodology is required to develop SoC devices that contain a billion or more transistors organised in tens or even hundreds of IP blocks.

Traditional on-chip bus architectures are becoming a bottleneck for two reasons. First, bus architectures need to continually evolve to keep pace with the ever-increasing complexity of SoC devices, which means that the bus interface in each IP block needs to be frequently modified, which increases the time-to-market of new SoC solutions. The second is that rather than behaving like transistors and scaling down in accordance with Moore's law, interconnections in each new technology generation, become more complex as they need to connect more on-chip functions with the result that cost/performance factors such as silicon area, on-chip communications speed and overall power consumption are increasingly dominated by the bus. In the long term, techniques such as optical intra-chip communications, in which ST has already reported world-leading R&D results, may eliminate this problem. In the medium term, new intra-chip interconnection technologies will be required to maintain the combination of price/performance/power improvements required by customers.

Industry experts widely view NoC technology as the solution. Essentially, NoC technology replaces the traditional circuit-switched bus by a packet-based paradigm incorporating a layered protocol stack analogous to a very simplified version of the networking paradigm. In this scenario, proven IP such as processor cores, cache memories, connectivity I/O functions, or specialized IP blocks such as audio/video codecs are simply plucked from a library, added to the SoC design and communicate with each other via a high-speed, low-power, small silicon area, packet-based communications protocol.

ST's proprietary "Spidergon" topology provides the industry's best price/performance trade-off for future SoC devices. In the Spidergon topology, all of the IP blocks are arranged in a ring and each IP block is connected to its clockwise and its counter-clockwise neighbour as in a simple polygonal ring topology. In addition, however, each IP block is also connected directly to its diagonal counterpart in the network, which allows the routing algorithm to minimise the number of nodes that a data packet has to traverse before reaching its destination. A particularly important benefit is that the functional diagram for a network of 16 connected nodes shown on the left of the image (Photo: http://www.newscom.com/cgi-bin/prnh/20051215/NYTH020 ) corresponds to a simple planar implementation shown on the right in which the wiring only needs to cross itself at one point. This is a key benefit in translating theoretical approaches into actual solutions that deliver the maximum price/performance benefits.

For this reason, the particular added value of Spidergon with respect to other proposed topologies is the ability to provide the proper cost/performance trade-off in the NoC domain. For example, topologies such as 2D-mesh that theoretically provide high communications speeds are expensive to implement in silicon because of their large number of router ports and connections; moreover the theoretically-offered connectivity can not be fully exploited in the on-chip domain due to the nature of communications traffic in real embedded applications. On the other hand, simple topologies such as rings are cost-effective in terms of manufacturing cost but deliver relatively poor intra-chip communication speed, especially as the number of IP blocks in the SoC increases, as it is certain to do in all application scenarios.

"For some time, the semiconductor industry has accepted that the future of SoC lies in NoC," said Alessandro Cremonesi, AST Vice President and Deputy General Manager, Systems Technology, STMicroelectronics. "The issue for SoC manufacturers is to deploy this emerging SoC design paradigm in an industry that is dominated by the need to minimize silicon area and design cycle times. With our Spidergon topology, we can freeze IP blocks into our libraries and put together any combination of IP that our customers require in a "plug and play" manner to rapidly develop SoC devices that deliver the industry's best combination of price and performance."

STNoC is a flexible and scalable packet-based on-chip micro-network designed according to a layered methodology. The most important feature of the Spidergon architecture is that the conceptual simplicity of the topology also translates into the most cost-effective silicon implementation of the key components: routers and network interfaces. Moreover, the specific Spidergon topology leads to a reduced set of homogeneous building blocks with well-controlled configurability, allowing for a substantial reduction in verification time and easier (fewer people-hours) maintenance, support and integration, which is a key strategic requirement.

STNoC technology delivers significant advantages to system designers, including the inherent cost-effectiveness of minimal silicon area and wiring complexity, and the ability to focus on the application, leveraging a powerful Quality of Service (QoS) support, without having to evaluate different network topologies for each application. Another important benefit is that STNoC's Network Interface allows any kind of IP protocol such as AXI, OCP, or STBus to be converted into communication packets. The ability to downsize the architecture by removing unused components and links depending on the application traffic allows STNoC to actually support a range of topologies, from the tree, to the simple ring and up to Spidergon topology.

Although a variety of NoC approaches have been proposed, STNoC is the only NoC technology that provides a full roadmap from current to future needs, thanks to its real performance/cost scalability. Current systems can benefit from wiring reduction, clean separation of end-to-end versus network tasks, multi-IP protocol support and efficient QoS, while future advanced multi-processor architectures can be defined on top of the sophisticated, flexible features of STNoC that deliver high-performance and reliable interconnection in the most cost-effective manner.

"The current SoC design paradigm will be good for a few more years but it will soon run out of steam," said Cremonesi. "NoC technology will clearly be the next wave in SoC but many of the proposed approaches fail to acknowledge the commercial realities of SoC design and manufacturing. ST's Spidergon topology will deliver the best price/performance trade-off and maintain ST's leadership in the SoC market."

About STMicroelectronics

STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2004, the Company's net revenues were $8.76 billion and net earnings were $601 million. Further information on ST can be found at http://www.st.com.

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